This invention relates to a gate control circuit for current-type inverter apparatus formed of self-extinction devices connected in a bridge form.
A current-type inverter apparatus is known which, as shown in FIG. 1 is formed of gate turn-off thyristors (hereinafter, referred to as GTO) as self-extinction devices. This inverter apparatus is used to control the revolution speed of, for example, an induction motor as a load. Since the circuit construction of this inverter apparatus is well known, the operation thereof will be briefly described. An AC current from an AC power supply 1 is rectified by a converter 2 into a DC current, which is supplied through a reactor 3 to an inverter 4. The inverter 4 is of three-phase bridge configuration each arm of which is formed of a GTO, 41 to 46 and diode, D1 to D6, connected in series, respectively. The inverter 4 converts the DC current to a three-phase AC current and supplies it to a load 5. Phase advancing capacitors 6 are each connected in parallel between the phases of the load 5. A conventional gate control circuit 9 for controlling this inverter apparatus comprises a logic circuit 7 and a gate amplifier 8 and controls the frequency of the inverter corresponding to the speed of the load 5, for example, an induction motor. A voltage signal, or frequency command signal corresponding to the inverter frequency is applied to the logic circuit which produces gate signals for turning on or off each self-extinction device, and the gate signals are amplified by the gate amplifier and supplied to the gates.
The operation of the conventional gate control circuit at the time when current flow is commutated from GTO 41 into GTO 42 will be described with reference to FIGS. 1 and 2.
When a frequency command signal is applied to the logic circuit 7, the logic circuit 7 produces a group of pulses of frequency corresponding to the input voltage thereto and the pulse is divided by a frequency divider (not shown) at, for example, 120.degree.-phase angle, so that six rectangular pulses with their phases being shifted by 60.degree. are produced. These 6 pulses are applied through a waveform shaping circuit (not shown) to the gate amplifier 8 where they are amplified, and the amplified signals are applied to the gates of the GTOs of the inverter 4. The waveforms of the output signals from the logic circuit 7 are ideally shown in FIG. 2. In this case, the GTO 41 is turned off and at the same time the GTO 42 is turned on, thus current flow being smoothly commutated from GTO 41 into GTO 42. In practice, however, when as shown in FIG. 3a, the output P.sub.41 from the logic circuit 7 for turning off the GTO 41 at time T.sub.0 is changed from high level to low level, the output P.sub.42 from the logic circuit 7 for turning on the GTO 42 will be delayed for the time T.sub.L to change from low level to high level as shown in FIG. 3a. The delay time T.sub.L is due to the operation delay characteristic of the logic elements, for example, TTL and caused when a plurality of different-mode logic output signals are produced from one frequency command signal.
Similarly, in the gate amplifier 8, signals are delayed in their transmission, that is, the output signals P41 and P42 from the logic circuit 7 are delayed T.sub.G1 and T.sub.G2 by the gate amplifier 8 as shown in FIG. 3b and then supplied as gate control signals P41' and P42' to the gates of the GTOs 41 and 42 respectively. The GTOs 41 and 42 delay the gate control signals by T.sub.OFF or T.sub.ON when they are turned off or on, respectively as shown in FIG. 3c. That is, at time T.sub.0 the output signal P41 from the logic circuit 7 is reduced to a low level and then when in practice the GTO 41 is turned off at time T.sub.1 and GTO 42 turned on at time T.sub.2, with the relation EQU T.sub.1 =T.sub.0 +T.sub.G1 +T.sub.OFF .ltoreq.T.sub.0 +T.sub.L +T.sub.G2 +T.sub.ON =T.sub.2 ( 1)
both the GTOs 41 and 42 under commutating operation may be turned off in the shaded period in FIG. 3. During this period, the energy stored in the DC reactor 3 is discharged through a capacitor snubber circuit not shown, not through an arm main circuit. This snubber circuit is provided in parallel to each GTO in order to absorb the surge voltage generated between the anode and cathode of the GTO when the GTO is turned off. However, the capacitor of the snubber circuit is usually too small in capacity to absorb the discharge energy from the DC reactor 3. Thus, the capacitor of the snubber circuit is overcharged so that the voltage between the anode and cathode of the GTO exceeds an allowable voltage and breaks down the GTO.
To obviate the drawbacks of this conventional example, there was proposed a gate control circuit having a signal delay-and-shape circuit provided between the logic circuit and gate amplifier to delay the trailing edge of pulse by a predetermined time as is disclosed in Japanese Patent Publication No. 19665/82 published on Apr. 23, 1982 filed by Kitamura and assigned to TOKYO SHIBAURA DENKI INC.
In this gate control circuit, as shown in FIG. 4, pulse B is produced for each-phase self-extinction device in synchronism with the trailing edge of the gate pulse A, and the logical sum C of pulse B and pulse A is obtained, then the trailing edge of the gate pulse being delayed so that the two-self extinction devices under commutating operation are turned on together during a period of time and thereby prevented from turning off together. In this case, however, since the elements forming the signal delay-and-shape circuit are turned on and off at slightly irregular timings, the pulse B is risen with delay of just small time d in response to the leading edge of pulse A with the result that the pulse C has a thin slit, or deficient pulse is caused as shown in FIG. 4c. Thus, the self-extinction devices are supplied with on-signal at once before entering the complete off-condition and thereby may be broken down.